En

FCOL
Flip Chip on Leadframe FCOL

JCET offers Flip Chip on Leadframe (FCOL) package configurations, such as QFN and TSOT, with a full turnkey solution for FCOL from wafer bumping and assembly to final test. FCOL provides unique high current, high thermal performance in a cost effective chip scale package.

Key benefits

• Chip Scale Package Solution
  Die to package clearance minimum to 75um per side. Die to package area ratio up to 90%.
• Excellent Electrical Performance
  Standard round or round-oval mix copper pillar bump provides high current path (>1A with 100um CuP Bump) and lower Rdson as a result of direct die to leadframe connection.
• High Thermal Performance
   Exposed die or metal lid attach significantly improves thermal dissipation through both top and bottom package surfaces, with up to ΘJC 80% reduction.
• Shorter Assembly Cycle Time
   Simplified process could cut 3 days in standard assembly cycle time compared with WBQFN.
• Full Turnkey Service
  JCET provides 200mm/300mm wafer bumping services in multiple manufacture sites, along with flip chip assembly and final tests.


  
Flip Chip Quad Flat No-lead Package
  Flip Chip Thin Small Outline Transistor

Application

• DC-DC
• LED
• RF Switch
• LNA
• PMU
• AC-DC
• Bulk
• Boost
• PA-Audio


Advantages

• Routable Leadframe
• High Power
• Hybrid Interconnection
• Multiple Chips
• Heat Sink

Additional Resources

FCQFN Datasheet

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版权所有@江苏长电科技股份有限公司 保留一切权利 苏ICP备05082751号32028102000607

版权所有@江苏长电科技股份有限公司
保留一切权利
苏ICP备05082751号 32028102000607