JCET’s Package-on-Package (PoP) family includes a stackable flip chip BGA as the bottom PoP package (PoPb). PoPb is typically an application processor or a baseband device with land pads placed on the top periphery of the package surface to enable the stacking of a second FBGA or PoP top (PoPt) above. PoPt, with memory devices stacked within, is assembled, tested and yielded independently. The two packages are combined by reflowing together (usually performed simultaneously) on the application board to form PoP (Z-interconnection with solder ball).
PoP has emerged as the preferred approach to integrate memory and logic in many advanced mobile and handheld applications. The bottom logic package and top memory package can be assembled, tested and yielded independently. This business model is preferred by end users as they can leverage their usual suppliers for these device types independently and have the flexibility to match logic processor and memory to support different applications.
JCET has always been at the forefront of 3D packaging and stacked die packaging. The wire bonded bottom PoP package was developed and introduced into production years ago. The bottom fcPoP provides the advantage of denser design with larger die size and higher number of IOs within the same PoP package body size / form factor as compared to the wire bonded PoP version. In addition, the use of fcPoP allows for potentially lower PoPb package height, thus reducing the total package stacked height post SMT process. Improved device electrical performance can also be expected with the fcPoP package as with all other Flip Chip packages in comparison to wire bonded designs.
Molded Laser PoP (PoP-MLP) allows for further height reduction and the use of tight memory interface (MI) pitch down to 0.3mm. A next-generation molded laser PoP with exposed die (PoP-MLP-ED), results in further package height reduction compared to PoP-MLP and will enable maximum package heights below 0.7mm (including warpage).