Global Layout

Worldwide locations with six sites in Jiangyin, Chuzhou, Suqian, Singapore and Korea; and two major R&D centers in Singapore and mainland China

Sites Introduction

JCET D1

JCET BU JCAP-1

Binjiang Road
Floor Area:62,321 sqm/GFA:58,300 sqm
Bumping, wafer level pkg & test
Factory Certificate
  • ISO9001
  • TS16949
  • ISO14001
  • OHSAS18001
  • QC080000
  • SONY GP
  • ESD20.20
  • IEC17025
  • ISO10012

JCET D3

JCAP-2/xinshun、JSCC/SJsemi

Changshan Road
Floor Area:374,882 sqm/GFA:372,500 sqm
WLCSP, bumping, flip chip, Leaded, laminate, SiP, test and MIS
Factory Certificate
  • ISO9001
  • TS16949
  • ISO14001
  • QC080000
Factory Certificate
  • ISO 9001
  • ISO 14001
  • IATF 16949
  • OHSAS 18001

JCET D9

Century Avenue

Floor Area:169,263 sqm/GFA:85,000 sqm
Leaded, discrete package and test
Factory Certificate
  • ISO9001
  • TS16949
  • ISO14001
  • OHSAS18001
  • QC080000
  • ESD20.20
  • SONY GP

JCET D8

Purple Mountain Road

Floor Area:84,122 sqm/GFA:53,700 sqm
Power package and test
Factory Certificate
  • ISO9001
  • TS16949
  • ISO14001
  • OHSAS18001
  • QC080000
  • ESD20.20

SCS

5 Yishun Street

Floor Area:29,894 sqm/GFA:73,600 sqm
Advanced wafer level packaging, laminate, QFN & test
Factory Certificate
  • ISO 9001
  • ISO 14001
  • IATF 16949
  • OHSAS 18001
  • Sony GP

JSCK

SCK/JSCK

191 Jayumuyeok-ro Jung-gu, Incheon

Floor Area:110,117 sqm/GFA:110,200 sqm
SiP,Flip chip, BGA, CSP, stacked die, probe, assembly and final test
Factory Certificate
  • ISO 9001
  • ISO 14001
  • IATF 16949
  • OHSAS 18001
  • Sony GP
  • ISO 14001/JSCK

R&D room

STATS ChipPAC HQ R&D center

Singapore
Floor area 4750 sqm
Tel:65-6853-8030
Fax:65-6752-9589

JCET HQ R&D center

Jiangyin China
Floor area 6872 sqm
Tel:+86-510-86997519
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Copyright @ Jiangsu Changjiang Electronics Technology Co., Ltd 苏ICP备05082751号32028102000607

Copyright @ Jiangsu Changjiang Electronics Technology Co., Ltd
苏ICP备05082751号 32028102000607

Official Accounts of JCET