Full Turnkey Service

Advanced package & silicon co-design process achieves optimum solution at a lower cost

Wafer Bump
Experienced in a  wide range of wafer bump alloys and processes – Electroplated process for SnPb, Pb-free, and Cu pillar bumps
Full service wafer bumping with Polyimide/PBO dielectric options for wafer repassivation and redistribution layer (RDL)
Fine pitch bumps down to 0.35mm (array and peripheral)
Contact Us |  Customer |  Legal

Contact Us Customer Enquiry Legal

Copyright @ Jiangsu Changjiang Electronics Technology Co., Ltd 苏ICP备05082751号32028102000607

Copyright @ Jiangsu Changjiang Electronics Technology Co., Ltd
苏ICP备05082751号 32028102000607

Official Accounts of JCET