Bare Die fcPoP
Bare Die Flip Chip Package-on-Package

JCET’s Package-on-Package (PoP) family includes a stackable flip chip BGA as the bottom PoP package (PoPb). PoPb is typically an application processor or a baseband device with land pads placed on the top periphery of the package surface to enable the stacking of a second FBGA or PoP top (PoPt) above. PoPt, with memory devices stacked within, is assembled, tested and yielded independently. The two packages are combined by reflowing together (usually performed simultaneously) on the application board to form PoP (Z-interconnection with solder ball).


PoP has emerged as the preferred approach to integrate memory and logic in many advanced mobile and handheld applications. The bottom logic package and top memory package can be assembled, tested and yielded independently. This business model is preferred by end users as they can leverage their usual suppliers for these device types independently and have the flexibility to match logic processor and memory to support different applications.

JCET has always been at the forefront of 3D packaging and stacked die packaging. The wire bonded bottom PoP package was developed and introduced into production years ago. The bottom fcPoP provides the advantage of denser design with larger die size and higher number of IOs within the same PoP package body size / form factor as compared to the wire bonded PoP version. In addition, the use of fcPoP allows for potentially lower PoPb package height, thus reducing the total package stacked height post-SMT process. Improved device electrical performance can also be expected with the fcPoP package as with all other Flip Chip packages in comparison to wire bonded designs. Bare die fcPoP package offers the lowest cost PoP package type and can use down to 0.4mm memory interface (MI) pitch.


Pre-stacked fc PoPb + PoPt

• Stacking fully tested memory and logic packages eliminates known good die (KGD) issues
• Package-on-package stacking provides flexibility in mixing and matching IC technologies
• Enables assembly of larger dies in thinner Package-on-package stack up with top ball pitch finder than bare die option
• Enables Package-on-Package solutions with low cost BOM
• Devices can be procured from multiple manufacturing sources
• Meets accepted package and board level reliability standards for CSP
• CuOSP on bottom BGA and top memory interface pads
• Die thickness down to 70um qualified
• Supports 0.3mm minimum ball pitch on bottom/BGA pads and down to 0.3mm pitch on top memory interface pads of PoPb
• CuOSP with SOP-SAC305 and eutectic SnPb for Flip Chip pads
• Qualified and HVM in 45nm and 28nm FAB node with lead-free solder
• Both Capillary Underfill (CUF) and Molded Underfill (MUF) available
• MUF allows for increased cavity size and hence larger die size, with lower assembly cost solution
• Bottom PoP package thickness of 0.72mm max with 100um thick flip chip die and 4 layer BU substrate
• Molded laser PoP with exposed die (ED) with package thickness of 0.62mm max height under development
• Full in-house electrical, thermal and mechanical simulation and measurement capability
• Full in-house package and substrate design capability
• Turnkey solution including wafer bumping in both eutectic SnPb and lead-free solder



Application, baseband or multimedia processor for mobile handset and portable devices


Memory to support system and processor functions including DDR, Flash (NAND, NOR), SRAM and combinations thereof

Additonal Resources

PoP Datasheet                                             Bare Die fcPoP Datasheet

FiPoP Datasheet                                           Molded Laser fcPoP Datasheet

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