flip chip with Cu Pillar, BOL and Enhanced Processes (fcCuBE®)
A unique flip chip packaging technology that features Cu pillar bumps, Bond-on-Lead (BOL) interconnection and Enhanced assembly processes for a proven, low cost, high performance solution.
Low Cost Flip Chip Solutions
fcCuBE® is a patented technology pioneered by JCET nearly ten years ago that squarely addresses the requirements of performance, form factor and cost in the mobile, consumer and cloud computing markets. With a powerful combination of copper (Cu) pillar bumps, patented Bond-on-Lead (BOL) interconnection and enhanced assembly processes, fcCuBE technology delivers higher input/output (I/O) density and performance at a lower cost. The advantages of fcCuBE technology are driving wider customer adoption from cost sensitive markets such as mobile and consumer to networking and cloud computing where increased routing density and performance are imperative.
fcCuBE® technology’s unique BOL interconnect structure provides scalability to very fine bump pitches and high I/O while alleviating stress-related chip to package interaction (CPI), a common phenomenon associated with lead free and copper pillar bump structures. This is particularly important for mid to high-end networking and consumer applications.
Scalability, Reliability, High Performance
In conjunction with higher performance copper pillar interconnect, fcCuBE® technology leverages JCET’s patented, routing-efficient BOL interconnection structure to expand the scalability of flip chip technology to ultra fine bump pitches (to ≤ 40µm) and higher I/O densities and eliminates stress on delicate ELK/ULK structures at advanced silicon wafer nodes. BOL further enables substrate design rule simplification, elimination of tight Solder Resist Registration (SRR) rules, and elimination of Solder-on-Pad (SOP). This combination of enhancements results in a high performance, low cost solution which also allows greater design flexibility and a streamlined manufacturing process. fcCuBE’s robust interconnect structure effectively alleviates thermo-mechanical stress which is a common phenomenon in advancecd Si node ELK/ULK die with Cu Pillar bump.
MR and TCB Options
A unique feature of fcCuBE® technology is the inherent compatibility of the basic design with both standard Mass Reflow (MR) assembly or Thermo-Compression Bonding (TCB). JCET’s uniquely developed MR process, which utilizes either Mold Underfill (MUF) or Capillary Underfill (CUF), supports bump pitches down to 80um and below, providing customers a lower cost alternative to TCB at these pitches. TCB is utilized for more complex face-to-back or face-to-face bonding of processes necessitated by Through Silicon Via (TSV) technology. Reflow method is determined by Si node, pitch, I/O design and product time to market.
ApplicationsfcCuBE® technology is a compelling solution for a wide cross section of end products in the low to high end mobile market, as well as mid to high end consumer and cloud computing markets:
ConfigurationsfcCuBE® technology is available across a wide range of platforms.